The present invention relates generally to phase-locked loop (PLL) circuits and, more particularly, to reducing lock re-acquisition time in a phase-locked loop (PLL) circuit.
Integrated circuits such as microprocessors, microcontroller units (MCUs), system-on-chips (SOCs), and application specific integrated circuits (ASICs) are widely used in portable devices including personal digital assistants (PDAs), tablet devices, and wireless communications devices. These devices use phase-locked loops (PLLs) that generate a clock signal based on an input reference signal. The clock signal has a phase and frequency that is directly proportional with the corresponding phase and frequency of the input reference signal. In integrated circuits (ICs), the clock signal generated by the PLL is used as a clock signal for synchronous operation of the internal circuitry.
FIG. 1 illustrates a schematic block diagram of a conventional PLL 100. The PLL 100 includes a voltage-controlled oscillator (VCO) 102, a frequency divider 104, a phase-frequency detector (PFD) 106, a charge pump 108 and a low pass filter (LPF) 110. The VCO 102 generates a clock signal having a frequency fout based on a control voltage Vctrl. The PFD 106 is connected to the VCO 102 by way of the frequency divider 104 and compares the phase of the clock signal with that of an input reference signal to generate an error signal based on a detected phase difference. The frequency divider 104 provides a fraction of the clock signal to the PFD 106. The charge pump 108 is connected to the PFD 106 and the VCO 102. The charge pump 108 receives the error signal and generates a charge pump current. The LPF 110, which is connected between the charge pump 108 and the VCO 102, receives the charge pump current and generates the control voltage Vctrlr which is then provided to the VCO 102, which in turn generates the clock signal having the frequency fout.
The clock signal generated by the PLL 100 is provided as a clock signal to an IC (not shown). ICs often are required to operate on a low supply voltage in order to consume as little battery power as possible, and hence are frequently switched from a RUN mode to a STOP mode during periods of inactivity. Wake-up circuitry is provided in the IC to switch the IC from the STOP mode to the RUN mode. The PLL 100 is switched OFF when the IC enters the STOP mode and is switched ON when the IC wakes up from the STOP mode and enters the RUN mode. After switching ON, the PLL 100 takes a finite amount of time to reach the lock frequency fout (referred to as PLL lock re-acquisition time). The PLL lock re-acquisition time adds to the wake-up time (time taken by the IC to transition from the STOP mode to the RUN mode) of the IC. A long wake-up time is undesirable, while a short wake-up time is especially useful when the IC performs time-critical applications.
Therefore, it would be advantageous to have a PLL with a fast PLL lock re-acquisition time.